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authorAlex Deucher <alexander.deucher@amd.com>2013-04-22 09:42:07 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-04-23 18:03:59 -0400
commit1586505a5db2b221a99feabe61199c2657e9ee23 (patch)
treec9bc5bd27a94af33687896d33a4aad346d0c6f1a /drivers/gpu/drm/radeon/r600_hdmi.c
parent46892caabe756228666d8d83aea5724d9557601a (diff)
drm/radeon: fix up audio dto programming for DCE2
Uses a different register than DCE3 asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_hdmi.c')
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c15
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 2e15888d8307..47f180a79352 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -246,9 +246,18 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
*/
- WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff);
- WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff);
- WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
+ if (ASIC_IS_DCE3(rdev)) {
+ /* according to the reg specs, this should DCE3.2 only, but in
+ * practice it seems to cover DCE3.0 as well.
+ */
+ WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 50);
+ WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
+ WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
+ } else {
+ /* according to the reg specs, this should be DCE2.0 and DCE3.0 */
+ WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate * 50) |
+ AUDIO_DTO_MODULE(clock * 100));
+ }
}
/*