diff options
| author | Jernej Skrabec <jernej.skrabec@siol.net> | 2018-03-01 22:34:37 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-03-02 08:45:40 +0100 |
| commit | 6876b160b70eeab5c7e0c3888f4907502a1df4a7 (patch) | |
| tree | 91cc800a950b485cd2cf55a710f49262feb15b44 /drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | |
| parent | 6fd903102c9d9e1c2807d5fbbf011b44f122b20d (diff) | |
drm/sun4i: Move and expand DW HDMI PHY register macros
DW HDMI PHY macros are moved to header file and expanded with the
registers present on newer SoCs like H3 and H5.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180301213442.16677-12-jernej.skrabec@siol.net
Diffstat (limited to 'drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c')
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index 17aada64bafd..16889bc0c62d 100644 --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c @@ -7,23 +7,6 @@ #include "sun8i_dw_hdmi.h" -#define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000 -#define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0) -#define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK GENMASK(15, 8) -#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC BIT(8) -#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC BIT(9) -#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK GENMASK(23, 16) -#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr) (addr << 16) - -#define SUN8I_HDMI_PHY_REXT_CTRL_REG 0x0004 -#define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN BIT(31) - -#define SUN8I_HDMI_PHY_READ_EN_REG 0x0010 -#define SUN8I_HDMI_PHY_READ_EN_MAGIC 0x54524545 - -#define SUN8I_HDMI_PHY_UNSCRAMBLE_REG 0x0014 -#define SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC 0x42494E47 - /* * Address can be actually any value. Here is set to same value as * it is set in BSP driver. |