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authorJernej Skrabec <jernej.skrabec@siol.net>2018-06-25 14:02:59 +0200
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-06-27 21:44:02 +0200
commitc891a65a7fc940ed387ad822732f711cae554b24 (patch)
tree513f5c86a788a040450770001caf5f6d6f31d14f /drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
parentaef13fd8426279fcd9e0b2b5b446d35c0d49ec5d (diff)
drm/sun4i: Add support for second clock parent to DW HDMI PHY clk driver
Expand HDMI PHY clock driver to support second clock parent. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-20-jernej.skrabec@siol.net
Diffstat (limited to 'drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c')
-rw-r--r--drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index f0877b3f67e7..aea46b08f127 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -491,7 +491,8 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
}
}
- ret = sun8i_phy_clk_create(phy, dev);
+ ret = sun8i_phy_clk_create(phy, dev,
+ phy->variant->has_second_pll);
if (ret) {
dev_err(dev, "Couldn't create the PHY clock\n");
goto err_put_clk_pll1;