diff options
| author | Thierry Reding <treding@nvidia.com> | 2015-07-21 16:33:48 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-28 11:18:44 +0100 |
| commit | c728e2d4a6546905f1179a8237860d8d276aaadc (patch) | |
| tree | f2d9a04f94615a5a73cc84f1371eeecf709675b2 /drivers/gpu/drm/tegra/dp.c | |
| parent | 1abd6b3304d47ff055063e0d59fc03bb27e0e196 (diff) | |
drm/tegra: dp: Track link capabilities alongside settings
Store capabilities in max_* fields and add separate fields for the
currently selected settings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dp.c')
| -rw-r--r-- | drivers/gpu/drm/tegra/dp.c | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index c19060b8753a..e55efd46a7d9 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -14,9 +14,12 @@ static void drm_dp_link_reset(struct drm_dp_link *link) return; link->revision = 0; - link->rate = 0; - link->num_lanes = 0; + link->max_rate = 0; + link->max_lanes = 0; link->capabilities = 0; + + link->rate = 0; + link->lanes = 0; } /** @@ -42,12 +45,15 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) return err; link->revision = values[0]; - link->rate = drm_dp_bw_code_to_link_rate(values[1]); - link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK; + link->max_rate = drm_dp_bw_code_to_link_rate(values[1]); + link->max_lanes = values[2] & DP_MAX_LANE_COUNT_MASK; if (values[2] & DP_ENHANCED_FRAME_CAP) link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; + link->rate = link->max_rate; + link->lanes = link->max_lanes; + return 0; } @@ -131,7 +137,7 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) int err; values[0] = drm_dp_link_rate_to_bw_code(link->rate); - values[1] = link->num_lanes; + values[1] = link->lanes; if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |