diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2023-10-16 09:34:53 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:43:00 -0500 |
| commit | 14a1e6a4a460fceae50fc1cf6b50d36c4ba96a7b (patch) | |
| tree | 86d68774777d2b45dfbb97c20c0c7dd95a054c38 /drivers/gpu/drm/xe/regs/xe_gpu_commands.h | |
| parent | e12a64881e97a78694012646cabd211399db8753 (diff) | |
drm/xe: Clarify number of dwords/qwords stored by MI_STORE_DATA_IMM
MI_STORE_DATA_IMM can store either dword values or qword values, and can
store more than one value if the instruction's length field is large
enough. Create explicit defines to specify the number of dwords/qwords
to be stored, which will set the instruction length correctly and, if
necessary, turn on the 'store qword' bit.
While we're here, also replace an open-coded version of
MI_STORE_DATA_IMM with the common macros.
Bspec: 60246
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231016163449.1300701-11-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs/xe_gpu_commands.h')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h index ad1e5466671b..8c2e0da694d8 100644 --- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h +++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h @@ -24,6 +24,9 @@ #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) #define MI_STORE_DATA_IMM MI_INSTR(0x20, 0) +#define MI_SDI_GGTT REG_BIT(22) +#define MI_SDI_NUM_DW(x) ((x) + 1) +#define MI_SDI_NUM_QW(x) (REG_BIT(21) | (2 * (x) + 1)) #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 0) #define MI_LRI_LRM_CS_MMIO REG_BIT(19) |