diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2023-06-01 14:52:43 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-19 18:34:27 -0500 |
| commit | 7bfbad97d38f1de4ffbc7d9dce6ee0128459293c (patch) | |
| tree | 3a395d18893135e586fc240c32a72873330ae6bc /drivers/gpu/drm/xe/regs/xe_gt_regs.h | |
| parent | 1bc728dcb8adc9f9e88f34940a94bfa314d4f7c3 (diff) | |
drm/xe: Reinstate media GT support
Now that tiles and GTs are handled separately and other prerequisite
changes are in place, we're ready to re-enable the media GT.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230601215244.678611-31-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs/xe_gt_regs.h')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index d8b480f69c5f..76c09526690e 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -8,6 +8,14 @@ #include "regs/xe_reg_defs.h" +/* + * The GSI register range [0x0 - 0x40000) is replicated at a higher offset + * for the media GT. xe_mmio and xe_gt_mcr functions will automatically + * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT. + */ +#define MEDIA_GT_GSI_OFFSET 0x380000 +#define MEDIA_GT_GSI_LENGTH 0x40000 + /* RPM unit config (Gen8+) */ #define RPM_CONFIG0 XE_REG(0xd00) #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3) |