diff options
| author | Vinay Belgaumkar <vinay.belgaumkar@intel.com> | 2024-07-01 16:15:29 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2024-07-02 12:14:00 -0400 |
| commit | aaa08078e7251131f045ba248a68671db7f7bdf7 (patch) | |
| tree | e944920e43981256db41d9ce544425a41969622d /drivers/gpu/drm/xe/xe_ggtt.c | |
| parent | b0b2b50cdbd132cb78ed25c27081849a405b75e3 (diff) | |
drm/xe/bmg: Apply Wa_22019338487
Extend this WA to BMG GT as well. In this case media GT is
not affected. The cap frequencies and max allowed ggtt writes
are different as well. On BMG, we need to do a flush after 1100
GGTT writes, and we need to limit the GT frequency request
to 2133 Mhz during driver load and leave it at that value after
driver unloads.
v3: Fix checkpatch issue
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240701231529.2582452-2-vinay.belgaumkar@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_ggtt.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_ggtt.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c index 883cfc7f98a8..0cdbc1296e88 100644 --- a/drivers/gpu/drm/xe/xe_ggtt.c +++ b/drivers/gpu/drm/xe/xe_ggtt.c @@ -74,6 +74,9 @@ static unsigned int probe_gsm_size(struct pci_dev *pdev) static void ggtt_update_access_counter(struct xe_ggtt *ggtt) { + struct xe_gt *gt = XE_WA(ggtt->tile->primary_gt, 22019338487) ? ggtt->tile->primary_gt : + ggtt->tile->media_gt; + u32 max_gtt_writes = XE_WA(ggtt->tile->primary_gt, 22019338487) ? 1100 : 63; /* * Wa_22019338487: GMD_ID is a RO register, a dummy write forces gunit * to wait for completion of prior GTT writes before letting this through. @@ -81,8 +84,8 @@ static void ggtt_update_access_counter(struct xe_ggtt *ggtt) */ lockdep_assert_held(&ggtt->lock); - if ((++ggtt->access_count % 63) == 0) { - xe_mmio_write32(ggtt->tile->media_gt, GMD_ID, 0x0); + if ((++ggtt->access_count % max_gtt_writes) == 0) { + xe_mmio_write32(gt, GMD_ID, 0x0); ggtt->access_count = 0; } } @@ -218,7 +221,9 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt) ggtt->size = GUC_GGTT_TOP; if (GRAPHICS_VERx100(xe) >= 1270) - ggtt->pt_ops = ggtt->tile->media_gt && XE_WA(ggtt->tile->media_gt, 22019338487) ? + ggtt->pt_ops = (ggtt->tile->media_gt && + XE_WA(ggtt->tile->media_gt, 22019338487)) || + XE_WA(ggtt->tile->primary_gt, 22019338487) ? &xelpg_pt_wa_ops : &xelpg_pt_ops; else ggtt->pt_ops = &xelp_pt_ops; |