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authorMichal Wajdeczko <michal.wajdeczko@intel.com>2024-09-02 21:29:53 +0200
committerMichal Wajdeczko <michal.wajdeczko@intel.com>2024-09-05 18:09:24 +0200
commit13a48a0fa52352f9fe58e2e1927670dcfea64c3a (patch)
tree51e171281bdcb2bc03d152ff1a2a12e9145370ea /drivers/gpu/drm/xe/xe_guc_ct.c
parent34bb7b813ab398106f700b0a6b218509bb0b904c (diff)
drm/xe/pf: Sanitize VF scratch registers on FLR
Some VF accessible registers (like GuC scratch registers) must be explicitly reset during the FLR. While this is today done by the GuC firmware, according to the design, this should be responsibility of the PF driver, as future platforms may require more registers to be reset. Likewise GuC, the PF can access VFs registers by adding some platform specific offset to the original register address. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240902192953.1792-1-michal.wajdeczko@intel.com
Diffstat (limited to 'drivers/gpu/drm/xe/xe_guc_ct.c')
0 files changed, 0 insertions, 0 deletions