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authorBadal Nilawar <badal.nilawar@intel.com>2023-10-25 21:42:01 +0530
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-21 11:43:22 -0500
commit8a93b0b4d1105b7d03b4768f1a08145b24cbd52a (patch)
tree7385aea8e96ad0f104280378ff37868f2ecf5c30 /drivers/gpu/drm/xe/xe_guc_pc.c
parent83af834e711ce779afb1ee6a28977b3e4b164354 (diff)
drm/xe: Extend rpX values extraction for future platforms
In existing code flow for future platforms i.e. >1270, the rpX (rp0,rpn and rpe) fused values are read from gen 6 registers. Which is not correct. Unless specified gen 1270 regs should be valid for gen 1270+ platforms as well. Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_guc_pc.c')
-rw-r--r--drivers/gpu/drm/xe/xe_guc_pc.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index d9375d1d582f..74247e0d3674 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -340,7 +340,7 @@ static void pc_update_rp_values(struct xe_guc_pc *pc)
struct xe_gt *gt = pc_to_gt(pc);
struct xe_device *xe = gt_to_xe(gt);
- if (xe->info.platform == XE_METEORLAKE)
+ if (GRAPHICS_VERx100(xe) >= 1270)
mtl_update_rpe_value(pc);
else
tgl_update_rpe_value(pc);
@@ -365,7 +365,7 @@ static ssize_t freq_act_show(struct device *dev,
xe_device_mem_access_get(gt_to_xe(gt));
/* When in RC6, actual frequency reported will be 0. */
- if (xe->info.platform == XE_METEORLAKE) {
+ if (GRAPHICS_VERx100(xe) >= 1270) {
freq = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1);
freq = REG_FIELD_GET(MTL_CAGF_MASK, freq);
} else {
@@ -680,7 +680,7 @@ static void pc_init_fused_rp_values(struct xe_guc_pc *pc)
struct xe_gt *gt = pc_to_gt(pc);
struct xe_device *xe = gt_to_xe(gt);
- if (xe->info.platform == XE_METEORLAKE)
+ if (GRAPHICS_VERx100(xe) >= 1270)
mtl_init_fused_rp_values(pc);
else
tgl_init_fused_rp_values(pc);