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| author | Matt Roper <matthew.d.roper@intel.com> | 2023-12-14 10:47:07 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:46:17 -0500 |
| commit | aaa536a8877e61104ccb5ba5287beaa4e959539e (patch) | |
| tree | 0a725ecc757e77fe5703340fa6508dbbd7135117 /drivers/gpu/drm/xe/xe_ttm_vram_mgr.c | |
| parent | 93536c2bcfb2c3c5e9b53c83f333f57d9b632e83 (diff) | |
drm/xe: Re-sort GT register header
Keeping the register definitions sorted will make it easy to find
existing definitions and prevent accidental introduction of duplicate
definitions.
v2:
- Reorder FUSE3/FUSE4 registers and move GT0_PERF_LIMIT_REASONS /
MTL_MEDIA_PERF_LIMIT_REASONS to proper places. (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231214184659.2249559-17-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_ttm_vram_mgr.c')
0 files changed, 0 insertions, 0 deletions