diff options
| author | Shawn Guo <shawn.guo@linaro.org> | 2017-04-11 19:30:26 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2017-05-04 13:53:05 +0800 |
| commit | 6911498df901950d2b83ea707b3d00b1f6366fbc (patch) | |
| tree | 50403c1194d179c65be1596c71474ab51577236a /drivers/gpu/drm/zte/zx_vou_regs.h | |
| parent | cd4b298334ebc7b7bd0384c6c81de398c983c6e3 (diff) | |
drm: zte: add VGA driver support
It adds VGA driver support, which needs to configure corresponding VOU
interface in RGB_888 format, and thus the following changes are needed
on zx_vou.
- Rename the CSC block of Graphic Layer a bit to make it more specific,
and add CSC of Channel to support RGB output.
- Bypass Dither block for RGB output.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1491910226-7831-1-git-send-email-shawnguo@kernel.org
Diffstat (limited to 'drivers/gpu/drm/zte/zx_vou_regs.h')
| -rw-r--r-- | drivers/gpu/drm/zte/zx_vou_regs.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/zte/zx_vou_regs.h b/drivers/gpu/drm/zte/zx_vou_regs.h index c066ef123434..5a218351b497 100644 --- a/drivers/gpu/drm/zte/zx_vou_regs.h +++ b/drivers/gpu/drm/zte/zx_vou_regs.h @@ -13,13 +13,17 @@ /* Sub-module offset */ #define MAIN_GL_OFFSET 0x130 -#define MAIN_CSC_OFFSET 0x580 +#define MAIN_GL_CSC_OFFSET 0x580 +#define MAIN_CHN_CSC_OFFSET 0x6c0 #define MAIN_HBSC_OFFSET 0x820 +#define MAIN_DITHER_OFFSET 0x960 #define MAIN_RSZ_OFFSET 0x600 /* OTFPPU sub-module */ #define AUX_GL_OFFSET 0x200 -#define AUX_CSC_OFFSET 0x5d0 +#define AUX_GL_CSC_OFFSET 0x5d0 +#define AUX_CHN_CSC_OFFSET 0x710 #define AUX_HBSC_OFFSET 0x860 +#define AUX_DITHER_OFFSET 0x970 #define AUX_RSZ_OFFSET 0x800 #define OSD_VL0_OFFSET 0x040 @@ -78,6 +82,10 @@ #define CHN_INTERLACE_BUF_CTRL 0x24 #define CHN_INTERLACE_EN BIT(2) +/* Dither registers */ +#define OSD_DITHER_CTRL0 0x00 +#define DITHER_BYSPASS BIT(31) + /* TIMING_CTRL registers */ #define TIMING_TC_ENABLE 0x04 #define AUX_TC_EN BIT(1) |