diff options
| author | Matthew Brost <matthew.brost@intel.com> | 2023-04-05 16:20:03 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-19 18:31:38 -0500 |
| commit | 1c060057ec29e0305aa314c19a80090c21524faa (patch) | |
| tree | d80a1360b6767ad46c9db7e7872740ce7eedda76 /drivers/gpu/drm | |
| parent | ad55ead7f3c7b041dbf058a9c4b954be5929bb5e (diff) | |
drm/xe: Always write GEN12_RCU_MODE.GEN12_RCU_MODE_CCS_ENABLE for CCS engines
If CCS0 was fused we did not write this register thus CCS engine were
not enabled resulting in driver load failures.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_hw_engine.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index 63a4efd5edcc..4b56c35b988d 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -253,7 +253,7 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe) u32 ccs_mask = xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE); - if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask & BIT(0)) + if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask) xe_mmio_write32(hwe->gt, GEN12_RCU_MODE.reg, _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); |