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| author | Minghuan Lian <Minghuan.Lian@nxp.com> | 2017-07-05 14:59:01 +0800 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2017-08-31 16:19:34 +0100 |
| commit | 4dd5da65a39d9a0405304fdef0804afffece044b (patch) | |
| tree | 6ae8318a51d2af9a04b9400b80e2b31e687ba314 /drivers/gpu/drm | |
| parent | cb3421684ee778d60da26232bfea626dca2eb8db (diff) | |
irqchip/ls-scfg-msi: Add LS1046a MSI support
LS1046a includes 4 MSIRs, each MSIR is assigned a dedicate GIC
SPI interrupt and provides 32 MSI interrupts. Compared to previous
MSI, LS1046a's IBS(interrupt bit select) shift is changed to 2 and
total MSI interrupt number is changed to 128.
The patch adds structure 'ls_scfg_msir' to describe MSIR setting and
'ibs_shift' to store the different value between the SoCs.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/gpu/drm')
0 files changed, 0 insertions, 0 deletions