diff options
| author | Wenjing Liu <wenjing.liu@amd.com> | 2024-05-10 11:25:55 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-05-20 16:20:25 -0400 |
| commit | 6b7fd8306efbd406fca9e8d27b2c103f951760c8 (patch) | |
| tree | 1c4a2de39ff2e5e6a188f6e47d6f5c4af6df17d4 /drivers/gpu/drm | |
| parent | 5745cb2da6fe08899420d695ce436df0166e7807 (diff) | |
drm/amd/display: fix a typo which causes an incorrect ODM combine setup
[why]
A recent change for ODM combine refactor contains a typo which causes ODM
combine mode programmed incorrectly.
Reviewed-by: George Shen <george.shen@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index d085c9ff9d38..42c3c440ed89 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -854,7 +854,7 @@ enum dc_status dcn20_enable_stream_timing( opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads); for (i = 0; i < opp_cnt; i++) - opp_inst[opp_cnt] = opp_heads[i]->stream_res.opp->inst; + opp_inst[i] = opp_heads[i]->stream_res.opp->inst; odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false); last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true); |