drm/amd/display: Adjust code style for dmub_cmd.h

[Why&How]
Make some formatting changes and rearranging of definitions for consistency.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 81 insertions, 81 deletions

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 25b59accb843..50686fef97f5 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -464,7 +464,8 @@ union replay_hw_flags {
 };
 
 /**
- * DMUB visual confirm color
+ * DMUB feature capabilities.
+ * After DMUB init, driver will query FW capabilities prior to enabling certain features.
  */
 struct dmub_feature_caps {
 	/**
@@ -641,7 +642,7 @@ union dmub_fw_boot_options {
 		uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
 		uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
 		uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
-		uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */
+		uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */
 		/**< 1 if all root clock gating is enabled and low power memory is enabled*/
 		uint32_t power_optimization: 1;
 		uint32_t diag_env: 1; /* 1 if diagnostic environment */
@@ -788,6 +789,11 @@ enum dmub_gpint_command {
 	DMUB_GPINT__PSR_RESIDENCY = 9,
 
 	/**
+	 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
+	 */
+	DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
+
+	/**
 	 * DESC: Get REPLAY state from FW.
 	 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
 	 */
@@ -801,11 +807,6 @@ enum dmub_gpint_command {
 	 */
 	DMUB_GPINT__REPLAY_RESIDENCY = 14,
 
-
-	/**
-	 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
-	 */
-	DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
 	/**
 	 * DESC: Updates the trace buffer lower 32-bit mask.
 	 * ARGS: The new mask
@@ -991,8 +992,9 @@ enum dmub_cmd_type {
 	 * Command type used for all panel control commands.
 	 */
 	DMUB_CMD__PANEL_CNTL = 74,
+
 	/**
-	 * Command type used for <TODO:description>
+	 * Command type used for all CAB commands.
 	 */
 	DMUB_CMD__CAB_FOR_SS = 75,
 
@@ -1017,7 +1019,6 @@ enum dmub_cmd_type {
 	/**
 	 * Command type used for all VBIOS interface commands.
 	 */
-
 	/**
 	 * Command type used for all REPLAY commands.
 	 */
@@ -1241,6 +1242,28 @@ struct dmub_rb_cmd_PLAT_54186_wa {
 };
 
 /**
+ * enum dmub_cmd_mall_type - MALL commands
+ */
+enum dmub_cmd_mall_type {
+	/**
+	 * Allows display refresh from MALL.
+	 */
+	DMUB_CMD__MALL_ACTION_ALLOW = 0,
+	/**
+	 * Disallows display refresh from MALL.
+	 */
+	DMUB_CMD__MALL_ACTION_DISALLOW = 1,
+	/**
+	 * Cursor copy for MALL.
+	 */
+	DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
+	/**
+	 * Controls DF requests.
+	 */
+	DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
+};
+
+/**
  * struct dmub_rb_cmd_mall - MALL command data.
  */
 struct dmub_rb_cmd_mall {
@@ -2079,28 +2102,6 @@ enum psr_version {
 };
 
 /**
- * enum dmub_cmd_mall_type - MALL commands
- */
-enum dmub_cmd_mall_type {
-	/**
-	 * Allows display refresh from MALL.
-	 */
-	DMUB_CMD__MALL_ACTION_ALLOW = 0,
-	/**
-	 * Disallows display refresh from MALL.
-	 */
-	DMUB_CMD__MALL_ACTION_DISALLOW = 1,
-	/**
-	 * Cursor copy for MALL.
-	 */
-	DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
-	/**
-	 * Controls DF requests.
-	 */
-	DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
-};
-
-/**
  * PHY Link rate for DP.
  */
 enum phy_link_rate {
@@ -2760,6 +2761,20 @@ struct dmub_cmd_psr_set_power_opt_data {
 	uint32_t power_opt;
 };
 
+/**
+ * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
+ */
+struct dmub_rb_cmd_psr_set_power_opt {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
+	 */
+	struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
+};
+
 #define REPLAY_RESIDENCY_MODE_SHIFT            (0)
 #define REPLAY_RESIDENCY_ENABLE_SHIFT          (1)
 
@@ -3049,20 +3064,6 @@ struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal {
 };
 
 /**
- * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
- */
-struct dmub_rb_cmd_psr_set_power_opt {
-	/**
-	 * Command header.
-	 */
-	struct dmub_cmd_header header;
-	/**
-	 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
-	 */
-	struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
-};
-
-/**
  * Set of HW components that can be locked.
  *
  * Note: If updating with more HW components, fields
@@ -3694,17 +3695,16 @@ struct dmub_rb_cmd_query_feature_caps {
  */
 struct dmub_cmd_visual_confirm_color_data {
 	/**
-	 * DMUB feature capabilities.
-	 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
+	 * DMUB visual confirm color
 	 */
-struct dmub_visual_confirm_color visual_confirm_color;
+	struct dmub_visual_confirm_color visual_confirm_color;
 };
 
 /**
  * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
  */
 struct dmub_rb_cmd_get_visual_confirm_color {
- /**
+	/**
 	 * Command header.
 	 */
 	struct dmub_cmd_header header;
@@ -3714,38 +3714,6 @@ struct dmub_rb_cmd_get_visual_confirm_color {
 	struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
 };
 
-struct dmub_optc_state {
-	uint32_t v_total_max;
-	uint32_t v_total_min;
-	uint32_t tg_inst;
-};
-
-struct dmub_rb_cmd_drr_update {
-		struct dmub_cmd_header header;
-		struct dmub_optc_state dmub_optc_state_req;
-};
-
-struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
-	uint32_t pix_clk_100hz;
-	uint8_t max_ramp_step;
-	uint8_t pipes;
-	uint8_t min_refresh_in_hz;
-	uint8_t pipe_count;
-	uint8_t pipe_index[4];
-};
-
-struct dmub_cmd_fw_assisted_mclk_switch_config {
-	uint8_t fams_enabled;
-	uint8_t visual_confirm_enabled;
-	uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
-	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
-};
-
-struct dmub_rb_cmd_fw_assisted_mclk_switch {
-	struct dmub_cmd_header header;
-	struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
-};
-
 /**
  * enum dmub_cmd_panel_cntl_type - Panel control command.
  */
@@ -3784,6 +3752,38 @@ struct dmub_rb_cmd_panel_cntl {
 	struct dmub_cmd_panel_cntl_data data; /**< payload */
 };
 
+struct dmub_optc_state {
+	uint32_t v_total_max;
+	uint32_t v_total_min;
+	uint32_t tg_inst;
+};
+
+struct dmub_rb_cmd_drr_update {
+	struct dmub_cmd_header header;
+	struct dmub_optc_state dmub_optc_state_req;
+};
+
+struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
+	uint32_t pix_clk_100hz;
+	uint8_t max_ramp_step;
+	uint8_t pipes;
+	uint8_t min_refresh_in_hz;
+	uint8_t pipe_count;
+	uint8_t pipe_index[4];
+};
+
+struct dmub_cmd_fw_assisted_mclk_switch_config {
+	uint8_t fams_enabled;
+	uint8_t visual_confirm_enabled;
+	uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
+	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
+};
+
+struct dmub_rb_cmd_fw_assisted_mclk_switch {
+	struct dmub_cmd_header header;
+	struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
+};
+
 /**
  * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
  */