diff options
| author | José Roberto de Souza <jose.souza@intel.com> | 2021-04-08 13:31:49 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-04-09 13:30:43 -0700 |
| commit | 61a60d7962a6e8ed94ece62764f94368cd6082b2 (patch) | |
| tree | 446226bd3be9880add3bfd1c680c91ed12a94680 /drivers/gpu | |
| parent | a844cfbe648d15d9f1031c45508c194f2d61c917 (diff) | |
drm/i915: Do not set any power wells when there is no display
Power wells are only part of display block and not necessary when
running a headless driver.
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210408203150.237947-2-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_power.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 9419ae8c6111..53311b9764dc 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4674,7 +4674,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) * The enabling order will be from lower to higher indexed wells, * the disabling order is reversed. */ - if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { + if (!HAS_DISPLAY(dev_priv)) { + power_domains->power_well_count = 0; + err = 0; + } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { err = set_power_wells_mask(power_domains, tgl_power_wells, BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); } else if (IS_ROCKETLAKE(dev_priv)) { |