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authorYabin Cui <yabinc@google.com>2023-01-27 23:10:01 +0000
committerSuzuki K Poulose <suzuki.poulose@arm.com>2023-01-30 11:45:32 +0000
commit669c4614236a7f78a2b693d0024cbdfa8536eb5a (patch)
treecb55e62d6c214593f8d43f74fe151067f0f372f8 /drivers/hwtracing/coresight/coresight-tmc-core.c
parentc88a15d9dd7dfabe2a13473fd1f9c4b9cd1b62c9 (diff)
coresight: tmc: Don't enable TMC when it's not ready.
If TMC ETR is enabled without being ready, in later use we may see AXI bus errors caused by accessing invalid addresses. Signed-off-by: Yabin Cui <yabinc@google.com> [ Tweak error message ] Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230127231001.1920947-1-yabinc@google.com
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-tmc-core.c')
-rw-r--r--drivers/hwtracing/coresight/coresight-tmc-core.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index 07abf28ad725..c106d142e632 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -31,7 +31,7 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb");
DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf");
DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr");
-void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
+int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
{
struct coresight_device *csdev = drvdata->csdev;
struct csdev_access *csa = &csdev->access;
@@ -40,7 +40,9 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
dev_err(&csdev->dev,
"timeout while waiting for TMC to be Ready\n");
+ return -EBUSY;
}
+ return 0;
}
void tmc_flush_and_stop(struct tmc_drvdata *drvdata)