Merge tag 'i2c-for-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Pull i2c updates from Wolfram Sang:
 "Core:

   - drivers can now use a GPIO as a side channel for SMBus Alerts using
     a generic binding

   - regular stuff like mem leak fix, Makefile maintenance...

  Host improvements and refactoring:

   - All controllers using the 'remove_new' callback have been reverted
     to use the 'remove' callback

   - Intel SCH controller underwent significant refactoring, this brings
     love and a modern look to the driver

   - PIIX4 driver refactored to enable usage by other drivers (e.g., AMD
     ASF)

   - iMX/MXC improved message handling to reduce protocol overhead:
     Refactored DMA/non-DMA read/write and bus polling mechanisms to
     achieve this.

   - ACPI documentation for PIIX4

  New host features:

   - i2c-cadence support for atomic transfers

   - Qualcomm CII support for a 32MHz serial engine clock

  Deprecated features:

   - Dropped outdated support for AMD756 S4882 and NFORCE2 S4985. If
     somebody misses this, Jean will rewrite support using the proper
     i2c mux framework.

  New hardware IDs for existing drivers:

   - Intel Panther Lake

   - S32G2/S32G3 SoCs

   - HJMC01 DesignWare ACPI HID

   - PIC64GX to Microchip Core

   - Qualcomm SDM670 to Qualcomm CCI

  New drivers:

   - AMD ASF

   - Realtek RTL I2C Controller

  at24 updates:

   - add support for the lockable page on ST M24256E"

* tag 'i2c-for-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (59 commits)
  docs: i2c: piix4: Add ACPI section
  i2c: Add driver for the RTL9300 I2C controller
  i2c: qcom-cci: Remove unused struct member cci_clk_rate
  dt-bindings: i2c: Add Realtek RTL I2C Controller
  i2c: busses: Use *-y instead of *-objs in Makefile
  i2c: imx: add support for S32G2/S32G3 SoCs
  dt-bindings: i2c: imx: add SoC specific compatible strings for S32G
  i2c: qcom-cci: Remove the unused variable cci_clk_rate
  i2c: Drop legacy muxing pseudo-drivers
  i2c: imx: prevent rescheduling in non dma mode
  i2c: imx: separate atomic, dma and non-dma use case
  i2c: imx: do not poll for bus busy in single master mode
  i2c: designware: Add a new ACPI HID for HJMC01 I2C controller
  i2c: qcom-geni: Keep comment why interrupts start disabled
  dt-bindings: i2c: microchip: corei2c: Add PIC64GX as compatible with driver
  i2c: designware: constify abort_sources
  i2c: Switch back to struct platform_driver::remove()
  i2c: qcom-geni: Support systems with 32MHz serial engine clock
  i2c: qcom-cci: Stop complaining about DT set clock rate
  dt-bindings: i2c: qcom-cci: Document SDM670 compatible
  ...

1 files changed, 4 insertions, 2 deletions

diff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses/i2c-designware-slave.c
index 7035296aa24c..fad568e3523b 100644
--- a/drivers/i2c/busses/i2c-designware-slave.c
+++ b/drivers/i2c/busses/i2c-designware-slave.c
@@ -32,12 +32,14 @@ static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev)
 }
 
 /**
- * i2c_dw_init_slave() - Initialize the designware i2c slave hardware
+ * i2c_dw_init_slave() - Initialize the DesignWare i2c slave hardware
  * @dev: device private data
  *
  * This function configures and enables the I2C in slave mode.
  * This function is called during I2C init function, and in case of timeout at
  * run time.
+ *
+ * Return: 0 on success, or negative errno otherwise.
  */
 static int i2c_dw_init_slave(struct dw_i2c_dev *dev)
 {
@@ -264,7 +266,7 @@ int i2c_dw_probe_slave(struct dw_i2c_dev *dev)
 	ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr_slave,
 			       IRQF_SHARED, dev_name(dev->dev), dev);
 	if (ret) {
-		dev_err(dev->dev, "failure requesting irq %i: %d\n",
+		dev_err(dev->dev, "failure requesting IRQ %i: %d\n",
 			dev->irq, ret);
 		return ret;
 	}