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authorLen Brown <len.brown@intel.com>2015-03-27 20:54:01 -0400
committerLen Brown <len.brown@intel.com>2015-03-31 21:57:15 -0400
commitcab07a5652d1d124b505c2b7ed21c6823295c5d7 (patch)
treed3944fd4847add04e7afb337ecb3d4e152ea7618 /drivers/idle/intel_idle.c
parentd7ef76717322c8e2df7d4360b33faa9466cb1a0d (diff)
intel_idle: Add support for the Airmont Core in the Cherrytrail and Braswell SOCs
Support C-states for the Airmont core in the Cherrytrail and Braswell SOCs. The states are similar to those of Silvermont in Baytrail, except both flavors of C6 states are faster. Signed-off-by: Len Brown <len.brown@intel.com> Cc: Kumar P Mahesh <mahesh.kumar.p@intel.com> Cc: Alan Cox <alan@linux.intel.com> Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/idle/intel_idle.c')
-rw-r--r--drivers/idle/intel_idle.c52
1 files changed, 52 insertions, 0 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 44d1d7920202..2ec8618c376f 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -253,6 +253,51 @@ static struct cpuidle_state byt_cstates[] = {
.enter = NULL }
};
+static struct cpuidle_state cht_cstates[] = {
+ {
+ .name = "C1-CHT",
+ .desc = "MWAIT 0x00",
+ .flags = MWAIT2flg(0x00),
+ .exit_latency = 1,
+ .target_residency = 1,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .name = "C6N-CHT",
+ .desc = "MWAIT 0x58",
+ .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 80,
+ .target_residency = 275,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .name = "C6S-CHT",
+ .desc = "MWAIT 0x52",
+ .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 200,
+ .target_residency = 560,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .name = "C7-CHT",
+ .desc = "MWAIT 0x60",
+ .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 1200,
+ .target_residency = 4000,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .name = "C7S-CHT",
+ .desc = "MWAIT 0x64",
+ .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 10000,
+ .target_residency = 20000,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .enter = NULL }
+};
+
static struct cpuidle_state ivb_cstates[] = {
{
.name = "C1-IVB",
@@ -740,6 +785,12 @@ static const struct idle_cpu idle_cpu_byt = {
.byt_auto_demotion_disable_flag = true,
};
+static const struct idle_cpu idle_cpu_cht = {
+ .state_table = cht_cstates,
+ .disable_promotion_to_c1e = true,
+ .byt_auto_demotion_disable_flag = true,
+};
+
static const struct idle_cpu idle_cpu_ivb = {
.state_table = ivb_cstates,
.disable_promotion_to_c1e = true,
@@ -782,6 +833,7 @@ static const struct x86_cpu_id intel_idle_ids[] = {
ICPU(0x2d, idle_cpu_snb),
ICPU(0x36, idle_cpu_atom),
ICPU(0x37, idle_cpu_byt),
+ ICPU(0x4c, idle_cpu_cht),
ICPU(0x3a, idle_cpu_ivb),
ICPU(0x3e, idle_cpu_ivt),
ICPU(0x3c, idle_cpu_hsw),