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authorJonathan Cameron <Jonathan.Cameron@huawei.com>2022-05-08 18:55:44 +0100
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2022-06-14 11:53:11 +0100
commite1f956a804df9074fb5de557563d153ae25252e7 (patch)
treeafcc5ab10fe7f4f45d11c7268e34e8d6f9b84c14 /drivers/iio/accel/adxl367.c
parent46403dcf3a7cbd24b86f809fd79962f4d6b137c5 (diff)
iio: accel: adxl367: Fix alignment for DMA safety
____cacheline_aligned is insufficient guarantee for non-coherent DMA. Switch to the updated IIO_DMA_MINALIGN definition. Update comment to reflect that DMA safety may require separate cachelines. Fixes: cbab791c5e2a5 ("iio: accel: add ADXL367 driver") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Cosmin Tanislav <demonsingur@gmail.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-5-jic23@kernel.org
Diffstat (limited to 'drivers/iio/accel/adxl367.c')
-rw-r--r--drivers/iio/accel/adxl367.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c
index 72a8c3fb27b9..47feb375b70b 100644
--- a/drivers/iio/accel/adxl367.c
+++ b/drivers/iio/accel/adxl367.c
@@ -179,7 +179,7 @@ struct adxl367_state {
unsigned int fifo_set_size;
unsigned int fifo_watermark;
- __be16 fifo_buf[ADXL367_FIFO_SIZE] ____cacheline_aligned;
+ __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN);
__be16 sample_buf;
u8 act_threshold_buf[2];
u8 inact_time_buf[2];