diff options
| author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2019-11-20 07:55:48 -0600 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2019-12-23 14:06:15 +0100 |
| commit | 813071438e83d338ba5cfe98b3b26c890dc0a6c0 (patch) | |
| tree | a5b3e71f7e71480ed2793d202e5ca54ebb166d00 /drivers/iommu/amd_iommu_types.h | |
| parent | 387caf0b759ac437a65ad5d59665558025f350fc (diff) | |
iommu/amd: Check feature support bit before accessing MSI capability registers
The IOMMU MMIO access to MSI capability registers is available only if
the EFR[MsiCapMmioSup] is set. Current implementation assumes this bit
is set if the EFR[XtSup] is set, which might not be the case.
Fix by checking the EFR[MsiCapMmioSup] before accessing the MSI address
low/high and MSI data registers via the MMIO.
Fixes: 66929812955b ('iommu/amd: Add support for X2APIC IOMMU interrupts')
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu/amd_iommu_types.h')
| -rw-r--r-- | drivers/iommu/amd_iommu_types.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index f52f59d5c6bd..f8a7945f3df9 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -383,6 +383,7 @@ /* IOMMU Extended Feature Register (EFR) */ #define IOMMU_EFR_XTSUP_SHIFT 2 #define IOMMU_EFR_GASUP_SHIFT 7 +#define IOMMU_EFR_MSICAPMMIOSUP_SHIFT 46 #define MAX_DOMAIN_ID 65536 |