diff options
| author | Bastien Curutchet <bastien.curutchet@bootlin.com> | 2024-12-04 10:43:15 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-12-09 20:37:07 +0100 |
| commit | a6d60e3376065752137ec23d103f7d039c363e41 (patch) | |
| tree | b054a3c0e28e1e13d37d23091f04a0c345da1100 /drivers/memory | |
| parent | 2c7b585d19cc1a7185a3a0b58cb643d28fd19cc1 (diff) | |
memory: ti-aemif: Create aemif_set_cs_timings()
Create an aemif_set_cs_timings() function to isolate the setting of a
chip select timing configuration and ease its exportation.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20241204094319.1050826-6-bastien.curutchet@bootlin.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'drivers/memory')
| -rw-r--r-- | drivers/memory/ti-aemif.c | 65 |
1 files changed, 49 insertions, 16 deletions
diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index ec770a2668e7..83fb308a831b 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -69,15 +69,15 @@ #define ACR_SSTROBE_MASK BIT(31) #define ASIZE_16BIT 1 -#define CONFIG_MASK (TA(TA_MAX) | \ - RHOLD(RHOLD_MAX) | \ - RSTROBE(RSTROBE_MAX) | \ - RSETUP(RSETUP_MAX) | \ - WHOLD(WHOLD_MAX) | \ - WSTROBE(WSTROBE_MAX) | \ - WSETUP(WSETUP_MAX) | \ - EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \ - ASIZE_MAX) +#define TIMINGS_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +#define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX) /** * struct aemif_cs_timings: structure to hold CS timings @@ -166,6 +166,44 @@ static int aemif_check_cs_timings(struct aemif_cs_timings *timings) } /** + * aemif_set_cs_timings() - Set the timing configuration of a given chip select. + * @aemif: aemif device to configure + * @cs: index of the chip select to configure + * @timings: timings configuration to set + * + * @return: 0 on success, else negative errno. + */ +static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_cs_timings *timings) +{ + unsigned int offset; + u32 val, set; + int ret; + + if (!timings || !aemif) + return -EINVAL; + + if (cs > aemif->num_cs) + return -EINVAL; + + ret = aemif_check_cs_timings(timings); + if (ret) + return ret; + + set = TA(timings->ta) | RHOLD(timings->rhold) | RSTROBE(timings->rstrobe) | + RSETUP(timings->rsetup) | WHOLD(timings->whold) | + WSTROBE(timings->wstrobe) | WSETUP(timings->wsetup); + + offset = A1CR_OFFSET + cs * 4; + + val = readl(aemif->base + offset); + val &= ~TIMINGS_MASK; + val |= set; + writel(val, aemif->base + offset); + + return 0; +} + +/** * aemif_calc_rate - calculate timing data. * @pdev: platform device to calculate for * @wanted: The cycle time needed in nanoseconds. @@ -213,12 +251,7 @@ static int aemif_config_abus(struct platform_device *pdev, int csnum) offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; - set = TA(data->timings.ta) | - RHOLD(data->timings.rhold) | RSTROBE(data->timings.rstrobe) | - RSETUP(data->timings.rsetup) | WHOLD(data->timings.whold) | - WSTROBE(data->timings.wstrobe) | WSETUP(data->timings.wsetup); - - set |= (data->asize & ACR_ASIZE_MASK); + set = (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) set |= ACR_EW_MASK; if (data->enable_ss) @@ -229,7 +262,7 @@ static int aemif_config_abus(struct platform_device *pdev, int csnum) val |= set; writel(val, aemif->base + offset); - return 0; + return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &data->timings); } /** |