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| author | Wenbin Mei <wenbin.mei@mediatek.com> | 2023-06-09 18:13:55 +0800 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2023-06-12 15:20:08 +0200 |
| commit | f2764e1f795c1db80ac1a08abae5b2f470355da6 (patch) | |
| tree | 40869e8d84d1e43f967c6de7d83379bc114738da /drivers/mmc/host/sdhci-pci-gli.c | |
| parent | ac93af1fe3f49ddecc6d0a367e9c3e1caac3cfe5 (diff) | |
mmc: mtk-sd: reduce CIT for better performance
CQHCI_SSC1 indicates to CQE the polling period to use when using periodic
SEND_QUEUE_STATUS(CMD13) polling.
Since MSDC CQE uses msdc_hclk as ITCFVAL, so driver should use hclk
frequency to get the actual time.
The default value 0x1000 that corresponds to 150us for MediaTek SoCs, let's
decrease it to 0x40 that corresponds to 2.35us, which can improve the
performance of some eMMC devices.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20230609101355.5220-2-wenbin.mei@mediatek.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/sdhci-pci-gli.c')
0 files changed, 0 insertions, 0 deletions