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authorJan Glauber <jglauber@cavium.com>2017-03-30 17:31:27 +0200
committerUlf Hansson <ulf.hansson@linaro.org>2017-04-24 21:42:11 +0200
commit4ce944074e5e2cb7ee48ff36608d65d0bc9c7647 (patch)
tree86b61b3a0e9b5e38dea17835851430445dc41537 /drivers/mmc/host
parentcd76e5c565e82af62f708120068ec5d226d98c95 (diff)
mmc: cavium: Support DDR mode for eMMC devices
Add support for switching to DDR mode for eMMC devices. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host')
-rw-r--r--drivers/mmc/host/cavium.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/mmc/host/cavium.c b/drivers/mmc/host/cavium.c
index eebb387dc8c4..d842b6986189 100644
--- a/drivers/mmc/host/cavium.c
+++ b/drivers/mmc/host/cavium.c
@@ -864,6 +864,10 @@ static void cvm_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
break;
}
+ /* DDR is available for 4/8 bit bus width */
+ if (ios->bus_width && ios->timing == MMC_TIMING_MMC_DDR52)
+ bus_width |= 4;
+
/* Change the clock frequency. */
clock = ios->clock;
if (clock > 52000000)
@@ -1032,8 +1036,14 @@ int cvm_mmc_of_slot_probe(struct device *dev, struct cvm_mmc_host *host)
/* Set up host parameters */
mmc->ops = &cvm_mmc_ops;
+ /*
+ * We only have a 3.3v supply, we cannot support any
+ * of the UHS modes. We do support the high speed DDR
+ * modes up to 52MHz.
+ */
mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
- MMC_CAP_ERASE | MMC_CAP_CMD23 | MMC_CAP_POWER_OFF_CARD;
+ MMC_CAP_ERASE | MMC_CAP_CMD23 | MMC_CAP_POWER_OFF_CARD |
+ MMC_CAP_3_3V_DDR;
if (host->use_sg)
mmc->max_segs = 16;