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authorDavid Daney <david.daney@cavium.com>2017-05-16 11:36:51 +0200
committerUlf Hansson <ulf.hansson@linaro.org>2017-05-19 09:17:44 +0200
commitaca69344c8a99e7374d913e42ba9120c398ee16f (patch)
tree4d3d8b8d19bf1319bf0bf5851f78478bf778027b /drivers/mmc/host
parentbae3dee0992dcb336a591468376b046e5447997b (diff)
mmc: cavium-octeon: Fix interrupt enable code
OCTEON SoCs with CIU3 do not have interrupt masking local to the MMC bus interface. Unfortunately, some even have a diagnostic register at the same address of the enable register, which causes the interrupts to fire immediately if stored to, thus breaking the driver. The proper action on these SoCs is not to touch this register. Fixes: 01d95843335c ("mmc: cavium: Add MMC support for Octeon SOCs.") Signed-off-by: David Daney <david.daney@cavium.com> [jglauber@cavium.com: removed point after subject line] Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host')
-rw-r--r--drivers/mmc/host/cavium-octeon.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/host/cavium-octeon.c b/drivers/mmc/host/cavium-octeon.c
index 772d0900026d..d698d66e3327 100644
--- a/drivers/mmc/host/cavium-octeon.c
+++ b/drivers/mmc/host/cavium-octeon.c
@@ -108,7 +108,7 @@ static void octeon_mmc_release_bus(struct cvm_mmc_host *host)
static void octeon_mmc_int_enable(struct cvm_mmc_host *host, u64 val)
{
writeq(val, host->base + MIO_EMM_INT(host));
- if (!host->dma_active || (host->dma_active && !host->has_ciu3))
+ if (!host->has_ciu3)
writeq(val, host->base + MIO_EMM_INT_EN(host));
}