summaryrefslogtreecommitdiff
path: root/drivers/mtd/nand/raw/nand_amd.c
diff options
context:
space:
mode:
authorBoris Brezillon <bbrezillon@kernel.org>2018-10-25 17:10:37 +0200
committerMiquel Raynal <miquel.raynal@bootlin.com>2019-04-08 10:21:12 +0200
commit629a442cad5facbebc204ff81e1974f8febab636 (patch)
treef24769f38c1fc76c8d6a1d06f08b3b621df361e7 /drivers/mtd/nand/raw/nand_amd.c
parent3020e30af6f81beedfeb4cf4eecc693bba55a6c2 (diff)
mtd: rawnand: Fill memorg during detection
If we want to use the generic NAND layer, we need to have the memorg struct appropriately filled. Patch the detection code to fill this struct. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'drivers/mtd/nand/raw/nand_amd.c')
-rw-r--r--drivers/mtd/nand/raw/nand_amd.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/mtd/nand/raw/nand_amd.c b/drivers/mtd/nand/raw/nand_amd.c
index 890c5b43e03c..e008fd662ee6 100644
--- a/drivers/mtd/nand/raw/nand_amd.c
+++ b/drivers/mtd/nand/raw/nand_amd.c
@@ -20,6 +20,9 @@
static void amd_nand_decode_id(struct nand_chip *chip)
{
struct mtd_info *mtd = nand_to_mtd(chip);
+ struct nand_memory_organization *memorg;
+
+ memorg = nanddev_get_memorg(&chip->base);
nand_decode_ext_id(chip);
@@ -31,9 +34,11 @@ static void amd_nand_decode_id(struct nand_chip *chip)
*/
if (chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 &&
chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 &&
- mtd->writesize == 512) {
- mtd->erasesize = 128 * 1024;
- mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1);
+ memorg->pagesize == 512) {
+ memorg->pages_per_eraseblock = 256;
+ memorg->pages_per_eraseblock <<= ((chip->id.data[3] & 0x03) << 1);
+ mtd->erasesize = memorg->pages_per_eraseblock *
+ memorg->pagesize;
}
}