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authorFlorian Fainelli <f.fainelli@gmail.com>2017-04-24 14:27:22 -0700
committerDavid S. Miller <davem@davemloft.net>2017-04-24 18:28:56 -0400
commit3fb22b0534e412569dd67dec625b4a051c7c2d7e (patch)
treecae0bc97044b2fad330017c14cc05d43f6091789 /drivers/net/dsa/b53/b53_regs.h
parenta424f0de61638cbb5047e0a888c54da9cf471f90 (diff)
net: dsa: b53: Implement software reset for 58xx devices
Implement the correct software reset sequence for 58xx devices by setting all 3 reset bits and polling for the SW_RST bit to clear itself without a given timeout. We cannot use is58xx() here because that would also include the 7445/7278 Starfighter 2 which have their own driver doing the reset earlier on due to the HW specific integration. Fixes: 991a36bb4645 ("net: dsa: b53: Add support for BCM585xx/586xx/88312 integrated switch") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/b53/b53_regs.h')
-rw-r--r--drivers/net/dsa/b53/b53_regs.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/dsa/b53/b53_regs.h b/drivers/net/dsa/b53/b53_regs.h
index f2a060e7a637..e5c86d44667a 100644
--- a/drivers/net/dsa/b53/b53_regs.h
+++ b/drivers/net/dsa/b53/b53_regs.h
@@ -143,6 +143,7 @@
/* Software reset register (8 bit) */
#define B53_SOFTRESET 0x79
#define SW_RST BIT(7)
+#define EN_CH_RST BIT(6)
#define EN_SW_RST BIT(4)
/* Fast Aging Control register (8 bit) */