diff options
author | Tobias Waldekranz <tobias@waldekranz.com> | 2022-01-28 17:26:49 +0100 |
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committer | David S. Miller <davem@davemloft.net> | 2022-01-31 11:29:12 +0000 |
commit | 35da1dfd94847c5f1ac04ce5b5002b888c3f36ec (patch) | |
tree | fdefec27b2f1a8e1052d89441b7b16a731a73202 /drivers/net/dsa/mv88e6xxx/chip.h | |
parent | 0da8aa00bfcfeb3f4e6537dd8e2001e0727ba549 (diff) |
net: dsa: mv88e6xxx: Improve performance of busy bit polling
Avoid a long delay when a busy bit is still set and has to be polled
again.
Measurements on a system with 2 Opals (6097F) and one Agate (6352)
show that even with this much tighter loop, we have about a 50% chance
of the bit being cleared on the first poll, all other accesses see the
bit being cleared on the second poll.
On a standard MDIO bus running MDC at 2.5MHz, a single access with 32
bits of preamble plus 32 bits of data takes 64*(1/2.5MHz) = 25.6us.
This means that mv88e6xxx_smi_direct_wait took 26us + CPU overhead in
the fast scenario, but 26us + 1500us + 26us + CPU overhead in the slow
case - bringing the average close to 1ms.
With this change in place, the slow case is closer to 2*26us + CPU
overhead, with the average well below 100us - a 10x improvement.
This translates to real-world winnings. On a 3-chip 20-port system,
the modprobe time drops by 88%:
Before:
root@coronet:~# time modprobe mv88e6xxx
real 0m 15.99s
user 0m 0.00s
sys 0m 1.52s
After:
root@coronet:~# time modprobe mv88e6xxx
real 0m 2.21s
user 0m 0.00s
sys 0m 1.54s
Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/mv88e6xxx/chip.h')
0 files changed, 0 insertions, 0 deletions