diff options
| author | Alexis Lothoré <alexis.lothore@bootlin.com> | 2023-05-29 10:02:43 +0200 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2023-05-30 23:54:33 -0700 |
| commit | 3ba89b28adb21a5d5d78e905e2c3972816606bb4 (patch) | |
| tree | 9ccd20c4f476d44e77b5580c2550c515e4475442 /drivers/net/dsa/mv88e6xxx/chip.h | |
| parent | 7a2dd00be869f0bcdcb13f4272913ba7371ab583 (diff) | |
net: dsa: mv88e6xxx: add field to specify internal phys layout
mv88e6xxx currently assumes that switch equipped with internal phys have
those phys mapped contiguously starting from port 0 (see
mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but
NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have
integrated PHYs available on ports 1 to 8
To properly support this offset, add a new field to allow specifying an
internal PHYs layout. If field is not set, default layout is assumed (start
at port 0)
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/dsa/mv88e6xxx/chip.h')
| -rw-r--r-- | drivers/net/dsa/mv88e6xxx/chip.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h index da6e1339f809..eca51946c100 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -167,6 +167,11 @@ struct mv88e6xxx_info { /* Supports PTP */ bool ptp_support; + + /* Internal PHY start index. 0 means that internal PHYs range starts at + * port 0, 1 means internal PHYs range starts at port 1, etc + */ + unsigned int internal_phys_offset; }; struct mv88e6xxx_atu_entry { |