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authorAndrew Lunn <andrew@lunn.ch>2019-02-08 22:25:44 +0100
committerDavid S. Miller <davem@davemloft.net>2019-02-09 19:02:36 -0800
commitec26016b953778c1727040adb98a0132b9162334 (patch)
tree470450ef43ad9311815db90facbdfe319baf1125 /drivers/net/dsa/mv88e6xxx
parent132c4e9e6ac5d97185b03529a062bdf9d14dcb9d (diff)
net: dsa: mv88e6xxx: SERDES support 2500BaseT via external PHY
By using an external PHY, ports 9 and 10 can support 2500BaseT. So set this link mode in the mask when validating. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/mv88e6xxx')
-rw-r--r--drivers/net/dsa/mv88e6xxx/chip.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 669a7f13fdce..39c780363764 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -647,8 +647,10 @@ static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
unsigned long *mask,
struct phylink_link_state *state)
{
- if (port >= 9)
+ if (port >= 9) {
phylink_set(mask, 2500baseX_Full);
+ phylink_set(mask, 2500baseT_Full);
+ }
/* No ethtool bits for 200Mbps */
phylink_set(mask, 1000baseT_Full);