diff options
| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-09-17 16:26:14 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-09-18 14:14:39 +0100 |
| commit | 1a9b5a26daf606868220f24b9783c0f37085454d (patch) | |
| tree | 76ecaa01745a60b9b6110fcb5d2a700d4436085e /drivers/net/ethernet/cadence/macb.h | |
| parent | d7b3485f1c2b917328890ba28f4e7cac4b98ca1e (diff) | |
net: macb: add support for mii on rgmii
Cadence IP has option to enable MII support on RGMII interface. This
could be selected though bit 28 of network control register. This option
is not enabled on all the IP versions thus add a software capability to
be selected by the proper implementation of this IP.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/cadence/macb.h')
| -rw-r--r-- | drivers/net/ethernet/cadence/macb.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index c33e98bfa5e8..5620b97b3482 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -246,6 +246,8 @@ #define MACB_SRTSM_OFFSET 15 /* Store Receive Timestamp to Memory */ #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */ #define MACB_OSSMODE_SIZE 1 +#define MACB_MIIONRGMII_OFFSET 28 /* MII Usage on RGMII Interface */ +#define MACB_MIIONRGMII_SIZE 1 /* Bitfields in NCFGR */ #define MACB_SPD_OFFSET 0 /* Speed */ @@ -713,6 +715,7 @@ #define MACB_CAPS_GEM_HAS_PTP 0x00000040 #define MACB_CAPS_BD_RD_PREFETCH 0x00000080 #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 +#define MACB_CAPS_MIIONRGMII 0x00000200 #define MACB_CAPS_CLK_HW_CHG 0x04000000 #define MACB_CAPS_MACB_IS_EMAC 0x08000000 #define MACB_CAPS_FIFO_MODE 0x10000000 |