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authorAnish Bhatt <anish@chelsio.com>2014-08-07 16:14:03 -0700
committerDavid S. Miller <davem@davemloft.net>2014-08-07 16:18:55 -0700
commit10b0046685ab410847f420d740acf604c8cb4eec (patch)
tree9701e13839a8cb4289eb6fbf404373f5b39009e0 /drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h
parenta1f7d81b735cdd682b0e7c81bb2c6821cbbf8060 (diff)
cxgb4: IEEE fixes for DCBx state machine
* Changes required due to 16eecd9be4b05 ("dcbnl : Fix misleading dcb_app->priority explanation") * Driver was previously not aware of what DCBx version was negotiated by firmware, this could lead to DCB app table in kernel or in firmware being populated wrong since IEEE/CEE used different formats made clear by above mentioned commit * Driver was missing a couple of state transitions that could be caused by other drivers that use chelsio hardware, resulting in incorrect behaviour (the change that addresses this also flips the state machine to switch on state instead of transition, hope this is okay in current window) * Prio queue info & tsa is no longer thrown away v2: Print DCBx state transition messages only when debug is enabled Signed-off-by: Anish Bhatt <anish@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h')
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h
index 1ec1d834e257..2a6aa88984f4 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h
@@ -63,6 +63,13 @@
#define INIT_PORT_DCB_WRITE_CMD(__pcmd, __port) \
INIT_PORT_DCB_CMD(__pcmd, __port, EXEC, FW_PORT_ACTION_L2_DCB_CFG)
+#define IEEE_FAUX_SYNC(__dev, __dcb) \
+ do { \
+ if ((__dcb)->dcb_version == FW_PORT_DCB_VER_IEEE) \
+ cxgb4_dcb_state_fsm((__dev), \
+ CXGB4_DCB_STATE_FW_ALLSYNCED); \
+ } while (0)
+
/* States we can be in for a port's Data Center Bridging.
*/
enum cxgb4_dcb_state {
@@ -108,11 +115,13 @@ struct port_dcb_info {
* Native Endian format).
*/
u32 pgid; /* Priority Group[0..7] */
+ u8 dcb_version; /* Running DCBx version */
u8 pfcen; /* Priority Flow Control[0..7] */
u8 pg_num_tcs_supported; /* max PG Traffic Classes */
u8 pfc_num_tcs_supported; /* max PFC Traffic Classes */
u8 pgrate[8]; /* Priority Group Rate[0..7] */
u8 priorate[8]; /* Priority Rate[0..7] */
+ u8 tsa[8]; /* TSA Algorithm[0..7] */
struct app_priority { /* Application Information */
u8 user_prio_map; /* Priority Map bitfield */
u8 sel_field; /* Protocol ID interpretation */
@@ -121,6 +130,7 @@ struct port_dcb_info {
};
void cxgb4_dcb_state_init(struct net_device *);
+void cxgb4_dcb_version_init(struct net_device *);
void cxgb4_dcb_state_fsm(struct net_device *, enum cxgb4_dcb_state_input);
void cxgb4_dcb_handle_fw_update(struct adapter *, const struct fw_port_cmd *);
void cxgb4_dcb_set_caps(struct adapter *, const struct fw_port_cmd *);