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authorVishal Kulkarni <vishal@chelsio.com>2019-05-22 21:46:12 +0530
committerDavid S. Miller <davem@davemloft.net>2019-05-22 17:35:14 -0700
commit74dd5aa1ed94a8099a57bb7f91300668d0600ade (patch)
tree5a153207975fea9d536cb604e5c076c8d2d6e9f0 /drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
parent2bb0f3b4341b0120d50ec11939fcbccdf6511fe6 (diff)
cxgb4: Enable hash filter with offload
Hash (exact-match) filters used for offloading flows share the same active region resources on the chip with upper layer drivers, like iw_cxgb4, chcr, etc. Currently, only either Hash filters or ULDs can use the active region resources, but not both. Hence, use the new firmware configuration parameters (when available) to allow both the Hash filters and ULDs to share the active region simultaneously. Signed-off-by: Vishal Kulkarni <vishal@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h')
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
index b2a618e72fcf..6a10e953fc40 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
@@ -1250,10 +1250,12 @@ enum fw_params_param_dev {
FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C,
FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E,
+ FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F,
FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20,
FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24,
FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
+ FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28,
FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29,
FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A,
};