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authorfrançois romieu <romieu@fr.zoreil.com>2012-04-17 11:11:40 +0000
committerDavid S. Miller <davem@davemloft.net>2012-04-17 22:54:13 -0400
commit0c20494050a848af4479dbaa89e632a8c5903cf3 (patch)
treebd869102a3f5f6b071d097e756b5e0293572f61c /drivers/net/ethernet/dec
parent584c5e2ad3ada1a5ccfffa68347b79c3681cc36e (diff)
dmfe: enforce consistent timing delay.
The driver does not always use the same timing for what looks like the same operations. - DCR0 Use the same udelay everywhere for reset. Upper bound is 100 us. - DCR9 Use 5us delay for srom clock. 1us delay for phy_write_1bit (writes PHY_DATA_[01]) are not changed as they stay withing a 2,5MHz MDIO clock range. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/dec')
-rw-r--r--drivers/net/ethernet/dec/tulip/dmfe.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/net/ethernet/dec/tulip/dmfe.c b/drivers/net/ethernet/dec/tulip/dmfe.c
index 0ef5b68acd05..4d6fe604fa64 100644
--- a/drivers/net/ethernet/dec/tulip/dmfe.c
+++ b/drivers/net/ethernet/dec/tulip/dmfe.c
@@ -767,7 +767,7 @@ static int dmfe_stop(struct DEVICE *dev)
/* Reset & stop DM910X board */
dw32(DCR0, DM910X_RESET);
- udelay(5);
+ udelay(100);
phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
/* free interrupt */
@@ -1601,7 +1601,9 @@ static u16 read_srom_word(void __iomem *ioaddr, int offset)
int i;
dw32(DCR9, CR9_SROM_READ);
+ udelay(5);
dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
+ udelay(5);
/* Send the Read Command 110b */
srom_clk_write(ioaddr, SROM_DATA_1);
@@ -1615,6 +1617,7 @@ static u16 read_srom_word(void __iomem *ioaddr, int offset)
}
dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
+ udelay(5);
for (i = 16; i > 0; i--) {
dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
@@ -1626,6 +1629,7 @@ static u16 read_srom_word(void __iomem *ioaddr, int offset)
}
dw32(DCR9, CR9_SROM_READ);
+ udelay(5);
return srom_data;
}