diff options
| author | Huazhong Tan <tanhuazhong@huawei.com> | 2021-05-14 11:25:09 +0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-05-14 15:07:33 -0700 |
| commit | 796640778c26f3d99fde173bb7b1d726b5f0d816 (patch) | |
| tree | d13f9583f86564eb5bf49d509d04ee3adb0c3b07 /drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | |
| parent | fc25f9f631acad4f4d0089fc400f2943c989522c (diff) | |
net: hns3: support RXD advanced layout
Currently, the driver gets packet type by parsing the
L3_ID/L4_ID/OL3_ID/OL4_ID from RX descriptor, it's
time-consuming.
Now some new devices support RXD advanced layout, which combines
previous OL3_ID/OL4_ID to 8bit ptype field, so the driver gets
packet type by looking up only one table, and L3_ID/L4_ID become
reserved fields.
Considering compatibility, the firmware will report capability of
RXD advanced layout, the driver will identify and enable it by
default. This patch provides basic function: identify and enable
the RXD advanced layout, and refactor out hns3_rx_checksum() by
using ptype table to handle RX checksum if supported.
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/hisilicon/hns3/hns3_enet.h')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h index daa04aeb0942..843642b9884b 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h @@ -19,6 +19,7 @@ enum hns3_nic_state { HNS3_NIC_STATE_SERVICE_SCHED, HNS3_NIC_STATE2_RESET_REQUESTED, HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, + HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, HNS3_NIC_STATE_MAX }; @@ -114,6 +115,9 @@ enum hns3_nic_state { #define HNS3_RXD_FBLI_S 14 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) +#define HNS3_RXD_PTYPE_S 4 +#define HNS3_RXD_PTYPE_M GENMASK(11, 4) + #define HNS3_RXD_BDTYPE_S 0 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) #define HNS3_RXD_VLD_B 4 @@ -366,6 +370,14 @@ enum hns3_pkt_ol4type { HNS3_OL4_TYPE_UNKNOWN }; +struct hns3_rx_ptype { + u32 ptype:8; + u32 csum_level:2; + u32 ip_summed:2; + u32 l3_type:4; + u32 valid:1; +}; + struct ring_stats { u64 sw_err_cnt; u64 seg_pkt_cnt; |