diff options
| author | Yunsheng Lin <linyunsheng@huawei.com> | 2019-06-28 19:50:09 +0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-06-28 09:39:49 -0700 |
| commit | 9e15be90b85a793815cae92aef80a2907a58bcfc (patch) | |
| tree | f24ffaa361340c93c8b4de91af5bc4239dcedcf8 /drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | |
| parent | ae179b2f05189844616ce629ec1e644ad52f35fd (diff) | |
net: hns3: change SSU's buffer allocation according to UM
Currently when there is share buffer in the SSU(storage
switching unit), the low waterline for RX private buffer is
too low to keep the hardware running. Hardware may have
processed all the packet stored in the private buffer of the
low waterline before the new packet comes, because hardware
only tell the peer send packet again when the private buffer
is under the low waterline.
So this patch only allocate RX private buffer if there is
enough buffer according to hardware user manual.
This patch also reserve some buffer for reusing when TC num
is less than or equal to 2, and change PAUSE_TRANS_GAP &
HCLGE_NON_DCB_ADDITIONAL_BUF according to hardware user
manual.
Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h index cf52cdf13270..d23ab2b819d9 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h @@ -884,7 +884,7 @@ struct hclge_serdes_lb_cmd { #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ -#define HCLGE_NON_DCB_ADDITIONAL_BUF 0x200 /* 512 byte */ +#define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */ #define HCLGE_TYPE_CRQ 0 #define HCLGE_TYPE_CSQ 1 |