diff options
| author | Todd Fujinaka <todd.fujinaka@intel.com> | 2014-07-10 01:47:15 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-07-10 01:48:28 -0700 |
| commit | 948264879b6894dc389a44b99fae4f0b72932619 (patch) | |
| tree | bcec9d0dd4a6ddca75038cbc44227fb25e05099e /drivers/net/ethernet/intel/igb/e1000_82575.c | |
| parent | b4df480f68ae03b5dd4ab0db56536fbcec741705 (diff) | |
igb: Workaround for i210 Errata 25: Slow System Clock
On some devices, the internal PLL circuit occasionally provides the
wrong clock frequency after power up. The probability of failure is less
than one failure per 1000 power cycles. When the failure occurs, the
internal clock frequency is around 1/20 of the correct frequency.
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Todd Fujinaka <todd.fujinaka@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/intel/igb/e1000_82575.c')
| -rw-r--r-- | drivers/net/ethernet/intel/igb/e1000_82575.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c index a2db388cc31e..ee74f9536b31 100644 --- a/drivers/net/ethernet/intel/igb/e1000_82575.c +++ b/drivers/net/ethernet/intel/igb/e1000_82575.c @@ -1481,6 +1481,13 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw) s32 ret_val; u16 i, rar_count = mac->rar_entry_count; + if ((hw->mac.type >= e1000_i210) && + !(igb_get_flash_presence_i210(hw))) { + ret_val = igb_pll_workaround_i210(hw); + if (ret_val) + return ret_val; + } + /* Initialize identification LED */ ret_val = igb_id_led_init(hw); if (ret_val) { |