diff options
| author | Antoine Tenart <antoine.tenart@bootlin.com> | 2019-08-12 16:45:34 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-08-15 16:31:11 -0700 |
| commit | 45bce1719cbd1ad3fb48f840accb1d120b6b0209 (patch) | |
| tree | 25311896df07ed90c4d86f078cd3dcc9ec5e2764 /drivers/net/ethernet/mscc/ocelot.h | |
| parent | 744350b98c3aa0295df84ce75603813a56423943 (diff) | |
net: mscc: describe the PTP register range
This patch adds support for using the PTP register range, and adds a
description of its registers. This bank is used when configuring PTP.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/mscc/ocelot.h')
| -rw-r--r-- | drivers/net/ethernet/mscc/ocelot.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h index f7eeb4806897..e0da8b4eddf2 100644 --- a/drivers/net/ethernet/mscc/ocelot.h +++ b/drivers/net/ethernet/mscc/ocelot.h @@ -23,6 +23,7 @@ #include "ocelot_sys.h" #include "ocelot_qs.h" #include "ocelot_tc.h" +#include "ocelot_ptp.h" #define PGID_AGGR 64 #define PGID_SRC 80 @@ -71,6 +72,7 @@ enum ocelot_target { SYS, S2, HSIO, + PTP, TARGET_MAX, }; @@ -343,6 +345,13 @@ enum ocelot_reg { S2_CACHE_ACTION_DAT, S2_CACHE_CNT_DAT, S2_CACHE_TG_DAT, + PTP_PIN_CFG = PTP << TARGET_OFFSET, + PTP_PIN_TOD_SEC_MSB, + PTP_PIN_TOD_SEC_LSB, + PTP_PIN_TOD_NSEC, + PTP_CFG_MISC, + PTP_CLK_CFG_ADJ_CFG, + PTP_CLK_CFG_ADJ_FREQ, }; enum ocelot_regfield { |