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authorjpinto <Joao.Pinto@synopsys.com>2016-12-23 10:15:59 +0000
committerDavid S. Miller <davem@davemloft.net>2016-12-23 11:46:37 -0500
commit567be786597ca24b13906a552ad2159316c6fe7d (patch)
tree8ca503b742460caa59d0ccc744a8181f4328533f /drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
parent2e3d5fa44f0f6e71ada2c4ed212ac23ca7ff0064 (diff)
stmmac: CSR clock configuration fix
When testing stmmac with my QoS reference design I checked a problem in the CSR clock configuration that was impossibilitating the phy discovery, since every read operation returned 0x0000ffff. This patch fixes the issue. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c')
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
index a1d582f47b1a..9dd2987e284d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
@@ -197,7 +197,7 @@ struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id)
mac->mii.reg_shift = 6;
mac->mii.reg_mask = 0x000007C0;
mac->mii.clk_csr_shift = 2;
- mac->mii.clk_csr_mask = 0xF;
+ mac->mii.clk_csr_mask = GENMASK(5, 2);
/* Synopsys Id is not available on old chips */
*synopsys_id = 0;