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authorJoao Pinto <Joao.Pinto@synopsys.com>2017-03-10 18:24:52 +0000
committerDavid S. Miller <davem@davemloft.net>2017-03-12 23:41:03 -0700
commitd0a9c9f9c6d0b1f0773e0aba5ab519b8ddc87a7a (patch)
tree76d6052caa3a52cda15c452f4e68db09310fed62 /drivers/net/ethernet/stmicro/stmmac/dwmac4.h
parentd976a525c371276cebd2517349d1d3568a0e48b5 (diff)
net: stmmac: configure mtl rx and tx algorithms
This patch adds the RX and TX scheduling algorithms programming. It introduces the multiple queues configuration function (stmmac_mtl_configuration) in stmmac_main. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac/dwmac4.h')
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac4.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index 018fc2d447c4..bc994fe3e6bf 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -164,6 +164,16 @@ enum power_event {
#define GMAC_HI_REG_AE BIT(31)
/* MTL registers */
+#define MTL_OPERATION_MODE 0x00000c00
+#define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5)
+#define MTL_OPERATION_SCHALG_WRR (0x0 << 5)
+#define MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
+#define MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
+#define MTL_OPERATION_SCHALG_SP (0x3 << 5)
+#define MTL_OPERATION_RAA BIT(2)
+#define MTL_OPERATION_RAA_SP (0x0 << 2)
+#define MTL_OPERATION_RAA_WSP (0x1 << 2)
+
#define MTL_INT_STATUS 0x00000c20
#define MTL_INT_Q0 BIT(0)