diff options
| author | Rohan G Thomas <rohan.g.thomas@intel.com> | 2023-12-01 13:52:50 +0800 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2023-12-04 18:37:39 -0800 |
| commit | 58f3240b3b93f880cae759ec2ff6ccfbf11903b7 (patch) | |
| tree | fe0b2449400775a7c12f0f384d69fbd9637c22df /drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | |
| parent | be5fc78a0084472dcc392cbea75f86202467437c (diff) | |
net: stmmac: xgmac: EST interrupts handling
Enabled the following EST related interrupts:
1) Constant Gate Control Error (CGCE)
2) Head-of-Line Blocking due to Scheduling (HLBS)
3) Head-of-Line Blocking due to Frame Size (HLBF)
4) Base Time Register error (BTRE)
5) Switch to S/W owned list Complete (SWLC)
Also, add EST errors into the ethtool statistic.
The commit e49aa315cb01 ("net: stmmac: EST interrupts handling and
error reporting") and commit 9f298959191b ("net: stmmac: Add EST
errors into ethtool statistic") add EST interrupts handling and error
reporting support to DWMAC4 core. This patch enables the same support
for XGMAC.
Signed-off-by: Rohan G Thomas <rohan.g.thomas@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20231201055252.1302-2-rohan.g.thomas@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h')
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index a4e8b498dea9..489f66094c49 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -289,6 +289,33 @@ #define XGMAC_PTOV_SHIFT 23 #define XGMAC_SSWL BIT(1) #define XGMAC_EEST BIT(0) +#define XGMAC_MTL_EST_STATUS 0x00001058 +#define XGMAC_BTRL GENMASK(15, 8) +#define XGMAC_BTRL_SHIFT 8 +#define XGMAC_BTRL_MAX GENMASK(15, 8) +#define XGMAC_CGCE BIT(4) +#define XGMAC_HLBS BIT(3) +#define XGMAC_HLBF BIT(2) +#define XGMAC_BTRE BIT(1) +#define XGMAC_SWLC BIT(0) +#define XGMAC_MTL_EST_SCH_ERR 0x00001060 +#define XGMAC_MTL_EST_FRM_SZ_ERR 0x00001064 +#define XGMAC_MTL_EST_FRM_SZ_CAP 0x00001068 +#define XGMAC_SZ_CAP_HBFS_MASK GENMASK(14, 0) +#define XGMAC_SZ_CAP_HBFQ_SHIFT 16 +#define XGMAC_SZ_CAP_HBFQ_MASK(val) \ + ({ \ + typeof(val) _val = (val); \ + (_val > 4 ? GENMASK(18, 16) : \ + _val > 2 ? GENMASK(17, 16) : \ + BIT(16)); \ + }) +#define XGMAC_MTL_EST_INT_EN 0x00001070 +#define XGMAC_IECGCE BIT(4) +#define XGMAC_IEHS BIT(3) +#define XGMAC_IEHF BIT(2) +#define XGMAC_IEBE BIT(1) +#define XGMAC_IECC BIT(0) #define XGMAC_MTL_EST_GCL_CONTROL 0x00001080 #define XGMAC_BTR_LOW 0x0 #define XGMAC_BTR_HIGH 0x1 |