diff options
| author | Grygorii Strashko <grygorii.strashko@ti.com> | 2023-12-19 12:58:03 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2023-12-23 01:01:19 +0000 |
| commit | bc8d62e16ec2f721f4edea12f2bbcf21405f43fa (patch) | |
| tree | ae00b7b3834d8e73f3b61a6f5de23d2b99c31f45 /drivers/net/ethernet/ti/Kconfig | |
| parent | 8f5a7561069853166cd735e46c449f203d61bf18 (diff) | |
net: ethernet: ti: am65-cpsw: add mqprio qdisc offload in channel mode
This patch adds MQPRIO Qdisc offload in full 'channel' mode which allows
not only setting up pri:tc mapping, but also configuring TX shapers
(rate-limiting) on external port FIFOs.
The MQPRIO Qdisc offload is expected to work with or without VLAN/priority
tagged packets.
The CPSW external Port FIFO has 8 Priority queues. The rate-limit can be
set for each of these priority queues. Which Priority queue a packet is
assigned to depends on PN_REG_TX_PRI_MAP register which maps header
priority to switch priority.
The header priority of a packet is assigned via the RX_PRI_MAP_REG which
maps packet priority to header priority.
The packet priority is either the VLAN priority (for VLAN tagged packets)
or the thread/channel offset.
For simplicity, we assign the same priority queue to all queues of a
Traffic Class so it can be rate-limited correctly.
Configuration example:
ethtool -L eth1 tx 5
ethtool --set-priv-flags eth1 p0-rx-ptype-rrobin off
tc qdisc add dev eth1 parent root handle 100: mqprio num_tc 3 \
map 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 \
queues 1@0 1@1 1@2 hw 1 mode channel \
shaper bw_rlimit min_rate 0 100mbit 200mbit max_rate 0 101mbit 202mbit
tc qdisc replace dev eth2 handle 100: parent root mqprio num_tc 1 \
map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 queues 1@0 hw 1
ip link add link eth1 name eth1.100 type vlan id 100
ip link set eth1.100 type vlan egress 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
In the above example two ports share the same TX CPPI queue 0 for low
priority traffic. 3 traffic classes are defined for eth1 and mapped to:
TC0 - low priority, TX CPPI queue 0 -> ext Port 1 fifo0, no rate limit
TC1 - prio 2, TX CPPI queue 1 -> ext Port 1 fifo1, CIR=100Mbit/s, EIR=1Mbit/s
TC2 - prio 3, TX CPPI queue 2 -> ext Port 1 fifo2, CIR=200Mbit/s, EIR=2Mbit/s
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/ti/Kconfig')
| -rw-r--r-- | drivers/net/ethernet/ti/Kconfig | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig index 49cd96c4f532..f76532443298 100644 --- a/drivers/net/ethernet/ti/Kconfig +++ b/drivers/net/ethernet/ti/Kconfig @@ -139,7 +139,8 @@ config TI_AM65_CPSW_QOS depends on TI_K3_AM65_CPSW_NUSS && NET_SCH_TAPRIO && TI_K3_AM65_CPTS help This option enables QoS offload features in AM65 CPSW like - Time Aware Shaper (TAS) / Enhanced Scheduled Traffic (EST). + Time Aware Shaper (TAS) / Enhanced Scheduled Traffic (EST) + and MQPRIO qdisc offload. The EST scheduler runs on CPTS and the TAS/EST schedule is updated in the Fetch RAM memory of the CPSW. |