summaryrefslogtreecommitdiff
path: root/drivers/net/tg3.c
diff options
context:
space:
mode:
authorMatt Carlson <mcarlson@broadcom.com>2011-05-19 12:12:46 +0000
committerDavid S. Miller <davem@davemloft.net>2011-05-19 18:00:00 -0400
commit1ff30a59f6d0c754e99442501a5145bdbbcfa6ea (patch)
tree28c1fb69dea98daba406fc07c6df0edd04cbbba5 /drivers/net/tg3.c
parent432aa7ed75b3adaef6040d2cbe745fdd1c899415 (diff)
tg3: Fix 57765 B0 data corruption
The PCIe max FTS limit is too aggressive on these chips. This patch loosens the limit a little to eliminate data corruption issues. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index b2b1ba168c88..09f2c11db247 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7990,6 +7990,22 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
tw32(GRC_MODE, grc_mode);
}
+ if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
+ u32 grc_mode = tr32(GRC_MODE);
+
+ /* Access the lower 1K of DL PCIE block registers. */
+ val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
+ tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
+
+ val = tr32(TG3_PCIE_TLDLPL_PORT +
+ TG3_PCIE_DL_LO_FTSMAX);
+ val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
+ tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
+ val | TG3_PCIE_DL_LO_FTSMAX_VAL);
+
+ tw32(GRC_MODE, grc_mode);
+ }
+
val = tr32(TG3_CPMU_LSPD_10MB_CLK);
val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
val |= CPMU_LSPD_10MB_MACCLK_6_25;