diff options
| author | Ping-Ke Shih <pkshih@realtek.com> | 2019-11-18 11:14:55 +0800 |
|---|---|---|
| committer | Kalle Valo <kvalo@codeaurora.org> | 2019-11-20 09:41:30 +0200 |
| commit | 4c8c0d8f709d16f418a5d1962b4eda86ff570151 (patch) | |
| tree | 538e6e6d69beb53aa467b82c532bfcc6063d1613 /drivers/net/wireless/realtek/rtlwifi/rtl8723com | |
| parent | 92541dd9dda5ab474751e24cdb4253eb290b8b33 (diff) | |
rtlwifi: set proper udelay within rf_serial_read
Since read RF register is an indirect access that hardware needs time to
accomplish read action, but there's no ready bit, so delay is required to
guarantee the read value is correct. After investigating internal documents,
these delays are reduced as proper values.
Reported-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Diffstat (limited to 'drivers/net/wireless/realtek/rtlwifi/rtl8723com')
| -rw-r--r-- | drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c index aae14c68bf69..debecc623a01 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c @@ -89,12 +89,10 @@ u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw, (newoffset << 23) | BLSSIREADEDGE; rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong & (~BLSSIREADEDGE)); - mdelay(1); rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); - mdelay(1); rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong | BLSSIREADEDGE); - mdelay(1); + udelay(120); if (rfpath == RF90_PATH_A) rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, BIT(8)); |