diff options
| author | Yan-Hsuan Chuang <yhchuang@realtek.com> | 2020-02-05 15:08:54 +0800 |
|---|---|---|
| committer | Kalle Valo <kvalo@codeaurora.org> | 2020-02-12 18:18:25 +0200 |
| commit | 2a4225551afbf8a0f8486c88a934f649766a186d (patch) | |
| tree | 65eae49249dbcfc4ee74f4ca24bf29c8b40a44d7 /drivers/net/wireless/realtek/rtw88/pci.c | |
| parent | 9e01c07069dbd0e025352d958c873a6504f8ce1b (diff) | |
rtw88: pci: 8822c should set clock delay to zero
Since RTL8822CE has enabled reference clock auto calibration,
there is no need to add any clock delay for covering the timing
gap of the reference clock.
Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Diffstat (limited to 'drivers/net/wireless/realtek/rtw88/pci.c')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw88/pci.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/wireless/realtek/rtw88/pci.c b/drivers/net/wireless/realtek/rtw88/pci.c index 1fbc14c149ec..9ac77aef708d 100644 --- a/drivers/net/wireless/realtek/rtw88/pci.c +++ b/drivers/net/wireless/realtek/rtw88/pci.c @@ -1197,11 +1197,18 @@ static void rtw_pci_link_ps(struct rtw_dev *rtwdev, bool enter) static void rtw_pci_link_cfg(struct rtw_dev *rtwdev) { + struct rtw_chip_info *chip = rtwdev->chip; struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; struct pci_dev *pdev = rtwpci->pdev; u16 link_ctrl; int ret; + /* RTL8822CE has enabled REFCLK auto calibration, it does not need + * to add clock delay to cover the REFCLK timing gap. + */ + if (chip->id == RTW_CHIP_TYPE_8822C) + rtw_dbi_write8(rtwdev, RTK_PCIE_CLKDLY_CTRL, 0); + /* Though there is standard PCIE configuration space to set the * link control register, but by Realtek's design, driver should * check if host supports CLKREQ/ASPM to enable the HW module. |