diff options
| author | Ping-Ke Shih <pkshih@realtek.com> | 2020-05-04 18:50:05 +0800 |
|---|---|---|
| committer | Kalle Valo <kvalo@codeaurora.org> | 2020-05-06 11:34:17 +0300 |
| commit | 5f028a9cf4b9e503151b25284384269beb0b742e (patch) | |
| tree | c0ea8117f07e3c5f7825484e3e4f663b6cb924cf /drivers/net/wireless/realtek/rtw88/rtw8723d.h | |
| parent | 158441a2bed49ea294cc79709bf88e17a7b71912 (diff) | |
rtw88: 8723d: Add set_channel
Set MAC/BB/RF register according to specified channel. The function
rtw_set_channel_mac() is used to set MAC registers, but 8723D only need
some of them.
For channel 14, we need to set different CCK DFIR values, so restore the
values when channel 1 to 13 is selected.
Spur calibration is needed in channel 13 and 14, and we do notch if spur
is over threshold.
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200504105010.10780-4-yhchuang@realtek.com
Diffstat (limited to 'drivers/net/wireless/realtek/rtw88/rtw8723d.h')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw88/rtw8723d.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723d.h b/drivers/net/wireless/realtek/rtw88/rtw8723d.h index 035049a29e7c..06614602de54 100644 --- a/drivers/net/wireless/realtek/rtw88/rtw8723d.h +++ b/drivers/net/wireless/realtek/rtw88/rtw8723d.h @@ -66,7 +66,38 @@ struct rtw8723d_efuse { #define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \ le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0)) +#define SPUR_THRES 0x16 +#define CCK_DFIR_NR 3 +#define DIS_3WIRE 0xccf000c0 +#define EN_3WIRE 0xccc000c0 +#define START_PSD 0x400000 +#define FREQ_CH13 0xfccd +#define FREQ_CH14 0xff9a +#define RFCFGCH_CHANNEL_MASK GENMASK(7, 0) +#define RFCFGCH_BW_MASK (BIT(11) | BIT(10)) +#define RFCFGCH_BW_20M (BIT(11) | BIT(10)) +#define RFCFGCH_BW_40M BIT(10) +#define BIT_MASK_RFMOD BIT(0) + +#define REG_PSDFN 0x0808 +#define REG_ANALOG_P4 0x088c +#define REG_PSDRPT 0x08b4 +#define REG_FPGA1_RFMOD 0x0900 +#define REG_BBRX_DFIR 0x0954 +#define BIT_MASK_RXBB_DFIR GENMASK(27, 24) +#define BIT_RXBB_DFIR_EN BIT(19) +#define REG_CCK0_SYS 0x0a00 +#define BIT_CCK_SIDE_BAND BIT(4) +#define REG_OFDM0_RXDSP 0x0c40 +#define BIT_MASK_RXDSP GENMASK(28, 24) +#define BIT_EN_RXDSP BIT(9) #define REG_OFDM0_XAAGC1 0x0c50 #define REG_OFDM0_XBAGC1 0x0c58 +#define REG_OFDM1_CFOTRK 0x0d2c +#define BIT_EN_CFOTRK BIT(28) +#define REG_OFDM1_CSI1 0x0d40 +#define REG_OFDM1_CSI2 0x0d44 +#define REG_OFDM1_CSI3 0x0d48 +#define REG_OFDM1_CSI4 0x0d4c #endif |