diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-31 16:00:01 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-11-21 16:25:39 -0600 |
| commit | fb26592301200dbbe4a9943fe188b57a46716900 (patch) | |
| tree | 5688b579fea3e33a47263646c4b24f914334b8e8 /drivers/pci/host/pcie-rockchip.c | |
| parent | 702ed3be1b1bf4dea05954168321741c0910c645 (diff) | |
PCI: Warn on possible RW1C corruption for sub-32 bit config writes
Hardware that supports only 32-bit config writes is not spec-compliant.
For example, if software performs a 16-bit write, we must do a 32-bit read,
merge in the 16 bits we intend to write, followed by a 32-bit write. If
the 16 bits we *don't* intend to write happen to have any RW1C (write-one-
to-clear) bits set, we just inadvertently cleared something we shouldn't
have.
Add a rate-limited warning when we do sub-32 bit config writes. Remove
similar probe-time warnings from some of the affected host bridge drivers.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Enthusiastically-Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com> # rockchip
Acked-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/pci/host/pcie-rockchip.c')
| -rw-r--r-- | drivers/pci/host/pcie-rockchip.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index e0b22dab9b7a..6419d8ca4a84 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -1187,9 +1187,6 @@ static int rockchip_pcie_probe(struct platform_device *pdev) pcie_bus_configure_settings(child); pci_bus_add_devices(bus); - - dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n"); - return err; err_vpcie: |