diff options
| author | Bharat Bhushan <bbhushan2@marvell.com> | 2022-02-11 10:23:44 +0530 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-03-08 11:17:37 +0000 |
| commit | 7cf83e222bce0f135f9c2714a49623cbb9fbde29 (patch) | |
| tree | 74aca2bf8c0215fa016e1253ba76bd6f51b4443c /drivers/perf/Makefile | |
| parent | 805bbdf28b271ed82b204cfd58b6eb456462ea49 (diff) | |
perf/marvell: CN10k DDR performance monitor support
Marvell CN10k DRAM Subsystem (DSS) supports eight event counters for
monitoring performance and software can program each counter to monitor
any of the defined performance event. Performance events are for
interface between the DDR controller and the PHY, interface between the
DDR Controller and the CHI interconnect, or within the DDR Controller.
Additionally DSS also supports two fixed performance event counters, one
for number of ddr reads and other for ddr writes.
This patch add basic support for these performance monitoring events
on CN10k.
Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
Reviewed-by: Bhaskara Budiredla <bbudiredla@marvell.com>
Link: https://lore.kernel.org/r/20220211045346.17894-3-bbhushan2@marvell.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/perf/Makefile')
| -rw-r--r-- | drivers/perf/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index 2db5418d5b0a..df52fb5ea2a6 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o obj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) += marvell_cn10k_tad_pmu.o +obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) += marvell_cn10k_ddr_pmu.o |