diff options
| author | David S. Miller <davem@davemloft.net> | 2020-03-12 21:29:30 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-03-12 22:34:48 -0700 |
| commit | 1d343579312311aa9875b34d5a921f5e2ec69f0a (patch) | |
| tree | 64b636b5557d92f5266187f035dac34862db86d5 /drivers/perf/fsl_imx8_ddr_perf.c | |
| parent | a8eceea84a3a3504e42f6495cf462027c5d19cb0 (diff) | |
| parent | 0d81a3f29c0afb18ba2b1275dcccf21e0dd4da38 (diff) | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Minor overlapping changes, nothing serious.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/perf/fsl_imx8_ddr_perf.c')
| -rw-r--r-- | drivers/perf/fsl_imx8_ddr_perf.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 95dca2cb5265..90884d14f95f 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -388,9 +388,10 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, if (enable) { /* - * must disable first, then enable again - * otherwise, cycle counter will not work - * if previous state is enabled. + * cycle counter is special which should firstly write 0 then + * write 1 into CLEAR bit to clear it. Other counters only + * need write 0 into CLEAR bit and it turns out to be 1 by + * hardware. Below enable flow is harmless for all counters. */ writel(0, pmu->base + reg); val = CNTL_EN | CNTL_CLEAR; @@ -398,7 +399,8 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, writel(val, pmu->base + reg); } else { /* Disable counter */ - writel(0, pmu->base + reg); + val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; + writel(val, pmu->base + reg); } } |