diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-03-16 11:24:51 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-03-16 11:24:51 -0700 |
| commit | 90a498f294c2766f05ba72dbc0ecafb2af521a4c (patch) | |
| tree | a63523273c5965ee84ff726617bfcf67a3308b9c /drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | |
| parent | 4438a810f3962a65d1d7259ee4195853a4d21a00 (diff) | |
| parent | 00ca8a15dafa990d391abc37f2b8256ddf909b35 (diff) | |
Merge tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"New hardware support:
- Qualcomm X1E80100 PCIe phy support, SM8550 PCIe1 PHY, SC7180 UFS
PHY and SDM630 USBC support
- Rockchip HDMI/eDP Combo PHY driver
- Mediatek MT8365 CSI phy driver
Updates:
- Rework on Qualcomm phy PCS registers and type-c handling
- Cadence torrent phy updates for multilink configuration
- TI gmii resume support"
* tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (41 commits)
phy: constify of_phandle_args in xlate
phy: ti: tusb1210: Define device IDs
phy: ti: tusb1210: Use temporary variable for struct device
phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver
dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema
phy: ti: gmii-sel: add resume support
phy: mtk-mipi-csi: add driver for CSI phy
dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink config for TI J7200
dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200
phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink configuration
phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configuration
dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1
phy: qcom-qmp-ufs: Switch to devm_clk_bulk_get_all() API
dt-bindings: phy: qmp-ufs: Fix PHY clocks
phy: qcom: sgmii-eth: move PCS registers to separate header
phy: qcom: sgmii-eth: use existing register definitions
phy: qcom: qmp-usbc: drop has_pwrdn_delay handling
phy: qcom: qmp: move common bits definitions to common header
phy: qcom: qmp: split DP PHY registers to separate headers
...
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h index 35d497fd9f9a..d9a87bd95590 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h @@ -15,13 +15,19 @@ #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24 #define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION 0x28 +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54 #define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1 0x58 #define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0 0xc4 #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4 #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0 +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4 #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc #define QSERDES_UFS_V6_RX_INTERFACE_MODE 0x1e0 +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214 @@ -33,6 +39,8 @@ #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264 #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270 #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280 +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284 #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8 #endif |